227 lines
8.4 KiB
C++
227 lines
8.4 KiB
C++
// This file is part of AsmJit project <https://asmjit.com>
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//
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// See asmjit.h or LICENSE.md for license and copyright information
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// SPDX-License-Identifier: Zlib
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#ifndef ASMJIT_ARM_ARMUTILS_H_INCLUDED
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#define ASMJIT_ARM_ARMUTILS_H_INCLUDED
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#include "../core/support.h"
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#include "../arm/armglobals.h"
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ASMJIT_BEGIN_SUB_NAMESPACE(arm)
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//! \addtogroup asmjit_arm
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//! \{
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//! Public utilities and helpers for targeting AArch32 and AArch64 architectures.
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namespace Utils {
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//! Encodes a 12-bit immediate part of opcode that ise used by a standard 32-bit ARM encoding.
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ASMJIT_MAYBE_UNUSED
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static inline bool encodeAArch32Imm(uint64_t imm, uint32_t* encodedImmOut) noexcept {
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if (imm & 0xFFFFFFFF00000000u)
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return false;
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uint32_t v = uint32_t(imm);
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uint32_t r = 0;
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if (v <= 0xFFu) {
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*encodedImmOut = v;
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return true;
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}
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// Rotate if there are bits on both ends (LSB and MSB)
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// (otherwise we would not be able to calculate the rotation with ctz).
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if (v & 0xFF0000FFu) {
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v = Support::ror(v, 16);
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r = 16u;
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}
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uint32_t n = Support::ctz(v) & ~0x1u;
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r = (r - n) & 0x1Eu;
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v = Support::ror(v, n);
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if (v > 0xFFu)
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return false;
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*encodedImmOut = v | (r << 7);
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return true;
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}
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//! Decomposed fields of a logical immediate value.
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struct LogicalImm {
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uint32_t n;
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uint32_t s;
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uint32_t r;
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};
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//! Encodes the given `imm` value of the given `width` to a logical immediate value represented as N, S, and R fields
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//! and writes these fields to `out`.
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//!
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//! Encoding Table:
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//!
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//! ```
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//! +---+--------+--------+------+
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//! | N | ImmS | ImmR | Size |
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//! +---+--------+--------+------+
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//! | 1 | ssssss | rrrrrr | 64 |
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//! | 0 | 0sssss | .rrrrr | 32 |
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//! | 0 | 10ssss | ..rrrr | 16 |
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//! | 0 | 110sss | ...rrr | 8 |
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//! | 0 | 1110ss | ....rr | 4 |
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//! | 0 | 11110s | .....r | 2 |
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//! +---+--------+--------+------+
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//! ```
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ASMJIT_MAYBE_UNUSED
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static bool encodeLogicalImm(uint64_t imm, uint32_t width, LogicalImm* out) noexcept {
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// Determine the element width, which must be 2, 4, 8, 16, 32, or 64 bits.
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do {
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width /= 2;
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uint64_t mask = (uint64_t(1) << width) - 1u;
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if ((imm & mask) != ((imm >> width) & mask)) {
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width *= 2;
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break;
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}
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} while (width > 2);
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// Patterns of all zeros and all ones are not encodable.
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uint64_t lsbMask = Support::lsbMask<uint64_t>(width);
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imm &= lsbMask;
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if (imm == 0 || imm == lsbMask)
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return false;
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// Inspect the pattern and get the most important bit indexes.
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//
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// oIndex <-+ +-> zIndex
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// | |
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// |..zeros..|oCount|zCount|..ones..|
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// |000000000|111111|000000|11111111|
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uint32_t zIndex = Support::ctz(~imm);
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uint64_t zImm = imm ^ ((uint64_t(1) << zIndex) - 1);
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uint32_t zCount = (zImm ? Support::ctz(zImm) : width) - zIndex;
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uint32_t oIndex = zIndex + zCount;
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uint64_t oImm = ~(zImm ^ Support::lsbMask<uint64_t>(oIndex));
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uint32_t oCount = (oImm ? Support::ctz(oImm) : width) - (oIndex);
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// Verify whether the bit-pattern is encodable.
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uint64_t mustBeZero = oImm ^ ~Support::lsbMask<uint64_t>(oIndex + oCount);
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if (mustBeZero != 0 || (zIndex > 0 && width - (oIndex + oCount) != 0))
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return false;
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out->n = width == 64;
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out->s = (oCount + zIndex - 1) | (Support::neg(width * 2) & 0x3F);
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out->r = width - oIndex;
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return true;
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}
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//! Returns true if the given `imm` value is encodable as a logical immediate. The `width` argument describes the
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//! width of the operation, and must be either 32 or 64. This function can be used to test whether an immediate
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//! value can be used with AND, ANDS, BIC, BICS, EON, EOR, ORN, and ORR instruction.
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ASMJIT_MAYBE_UNUSED
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static ASMJIT_INLINE_NODEBUG bool isLogicalImm(uint64_t imm, uint32_t width) noexcept {
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LogicalImm dummy;
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return encodeLogicalImm(imm, width, &dummy);
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}
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//! Returns true if the given `imm` value is encodable as an immediate with `add` and `sub` instructions on AArch64.
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//! These two instructions can encode 12-bit immediate value optionally shifted left by 12 bits.
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ASMJIT_MAYBE_UNUSED
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static ASMJIT_INLINE_NODEBUG bool isAddSubImm(uint64_t imm) noexcept {
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return imm <= 0xFFFu || (imm & ~uint64_t(0xFFFu << 12)) == 0;
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}
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//! Returns true if the given `imm` value is a byte mask. Byte mask has each byte part of the value set to either
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//! 0x00 or 0xFF. Some ARM instructions accept immediates that form a byte-mask and this function can be used to
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//! verify that the immediate is encodable before using the value.
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template<typename T>
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static ASMJIT_INLINE_NODEBUG bool isByteMaskImm8(const T& imm) noexcept {
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constexpr T kMask = T(0x0101010101010101 & Support::allOnes<T>());
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return imm == (imm & kMask) * T(255);
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}
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// [.......A|B.......|.......C|D.......|.......E|F.......|.......G|H.......]
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static ASMJIT_INLINE_NODEBUG uint32_t encodeImm64ByteMaskToImm8(uint64_t imm) noexcept {
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return uint32_t(((imm >> (7 - 0)) & 0b00000011) | // [.......G|H.......]
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((imm >> (23 - 2)) & 0b00001100) | // [.......E|F.......]
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((imm >> (39 - 4)) & 0b00110000) | // [.......C|D.......]
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((imm >> (55 - 6)) & 0b11000000)); // [.......A|B.......]
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}
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//! \cond
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//! A generic implementation that checjs whether a floating point value can be converted to ARM Imm8.
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template<typename T, uint32_t kNumBBits, uint32_t kNumCDEFGHBits, uint32_t kNumZeroBits>
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static ASMJIT_FORCE_INLINE bool isFPImm8Generic(T val) noexcept {
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constexpr uint32_t kAllBsMask = Support::lsbMask<uint32_t>(kNumBBits);
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constexpr uint32_t kB0Pattern = Support::bitMask(kNumBBits - 1);
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constexpr uint32_t kB1Pattern = kAllBsMask ^ kB0Pattern;
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T immZ = val & Support::lsbMask<T>(kNumZeroBits);
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uint32_t immB = uint32_t(val >> (kNumZeroBits + kNumCDEFGHBits)) & kAllBsMask;
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// ImmZ must be all zeros and ImmB must either be B0 or B1 pattern.
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return immZ == 0 && (immB == kB0Pattern || immB == kB1Pattern);
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}
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//! \endcond
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//! Returns true if the given half precision floating point `val` can be encoded as ARM IMM8 value, which represents
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//! a limited set of floating point immediate values, which can be used with FMOV instruction.
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//!
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//! The floating point must have bits distributed in the following way:
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//!
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//! ```
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//! [aBbbcdef|gh000000]
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//! ```
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static ASMJIT_INLINE_NODEBUG bool isFP16Imm8(uint32_t val) noexcept { return isFPImm8Generic<uint32_t, 3, 6, 6>(val); }
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//! Returns true if the given single precision floating point `val` can be encoded as ARM IMM8 value, which represents
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//! a limited set of floating point immediate values, which can be used with FMOV instruction.
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//!
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//! The floating point must have bits distributed in the following way:
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//!
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//! ```
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//! [aBbbbbbc|defgh000|00000000|00000000]
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//! ```
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static ASMJIT_INLINE_NODEBUG bool isFP32Imm8(uint32_t val) noexcept { return isFPImm8Generic<uint32_t, 6, 6, 19>(val); }
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//! \overload
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static ASMJIT_INLINE_NODEBUG bool isFP32Imm8(float val) noexcept { return isFP32Imm8(Support::bitCast<uint32_t>(val)); }
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//! Returns true if the given double precision floating point `val` can be encoded as ARM IMM8 value, which represents
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//! a limited set of floating point immediate values, which can be used with FMOV instruction.
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//!
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//! The floating point must have bits distributed in the following way:
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//!
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//! ```
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//! [aBbbbbbb|bbcdefgh|00000000|00000000|00000000|00000000|00000000|00000000]
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//! ```
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static ASMJIT_INLINE_NODEBUG bool isFP64Imm8(uint64_t val) noexcept { return isFPImm8Generic<uint64_t, 9, 6, 48>(val); }
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//! \overload
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static ASMJIT_INLINE_NODEBUG bool isFP64Imm8(double val) noexcept { return isFP64Imm8(Support::bitCast<uint64_t>(val)); }
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//! \cond
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template<typename T, uint32_t kNumBBits, uint32_t kNumCDEFGHBits, uint32_t kNumZeroBits>
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static ASMJIT_INLINE_NODEBUG uint32_t encodeFPToImm8Generic(T val) noexcept {
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uint32_t bits = uint32_t(val >> kNumZeroBits);
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return ((bits >> (kNumBBits + kNumCDEFGHBits - 7)) & 0x80u) | (bits & 0x7F);
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}
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//! \endcond
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//! Encodes a double precision floating point value into IMM8 format.
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//!
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//! \note This function expects that `isFP64Imm8(val) == true` so it doesn't perform any checks of the value and just
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//! rearranges some bits into Imm8 order.
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static ASMJIT_INLINE_NODEBUG uint32_t encodeFP64ToImm8(uint64_t val) noexcept { return encodeFPToImm8Generic<uint64_t, 9, 6, 48>(val); }
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//! \overload
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static ASMJIT_INLINE_NODEBUG uint32_t encodeFP64ToImm8(double val) noexcept { return encodeFP64ToImm8(Support::bitCast<uint64_t>(val)); }
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} // {Utils}
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//! \}
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ASMJIT_END_SUB_NAMESPACE
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#endif // ASMJIT_ARM_ARMUTILS_H_INCLUDED
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