262 lines
9.4 KiB
C++
262 lines
9.4 KiB
C++
// This file is part of AsmJit project <https://asmjit.com>
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//
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// See asmjit.h or LICENSE.md for license and copyright information
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// SPDX-License-Identifier: Zlib
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#ifndef ASMJIT_CORE_ARCHCOMMONS_H_INCLUDED
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#define ASMJIT_CORE_ARCHCOMMONS_H_INCLUDED
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// This file provides architecture-specific classes that are required in the core library. For example Imm operand
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// allows to be created from arm::Shift in a const-expr way, so the arm::Shift must be provided. So this header file
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// provides everything architecture-specific that is used by the Core API.
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#include "../core/globals.h"
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ASMJIT_BEGIN_SUB_NAMESPACE(arm)
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//! \addtogroup asmjit_arm
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//! \{
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//! Condition code (both AArch32 & AArch64).
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//!
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//! \note This enumeration doesn't match condition code that is used in AArch32/AArch64 opcodes. In general this
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//! condition code is encoded as `(cc - 2) & 0xF` so that `kAL` condition code is zero and encoded as 0xE in opcode.
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//! This makes it easier to use a condition code as an instruction modifier that defaults to 'al'.
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enum class CondCode : uint8_t {
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kAL = 0x00u, //!< (no condition code) (always)
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kNA = 0x01u, //!< (not available) (special)
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kEQ = 0x02u, //!< Z==1 (any_sign ==)
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kNE = 0x03u, //!< Z==0 (any_sign !=)
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kCS = 0x04u, //!< C==1 (unsigned >=)
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kHS = 0x04u, //!< C==1 (unsigned >=)
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kLO = 0x05u, //!< C==0 (unsigned < )
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kCC = 0x05u, //!< C==0 (unsigned < )
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kMI = 0x06u, //!< N==1 (is negative)
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kPL = 0x07u, //!< N==0 (is positive or zero)
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kVS = 0x08u, //!< V==1 (is overflow)
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kVC = 0x09u, //!< V==0 (no overflow)
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kHI = 0x0Au, //!< C==1 & Z==0 (unsigned > )
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kLS = 0x0Bu, //!< C==0 | Z==1 (unsigned <=)
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kGE = 0x0Cu, //!< N==V (signed >=)
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kLT = 0x0Du, //!< N!=V (signed < )
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kGT = 0x0Eu, //!< Z==0 & N==V (signed > )
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kLE = 0x0Fu, //!< Z==1 | N!=V (signed <=)
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kZero = kEQ, //!< Zero flag (alias to equal).
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kNotZero = kNE, //!< Not zero (alias to Not Equal).
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kEqual = kEQ, //!< Equal `a == b`.
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kNotEqual = kNE, //!< Not Equal `a != b`.
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kCarry = kCS, //!< Carry flag.
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kNotCarry = kCC, //!< Not carry.
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kSign = kMI, //!< Sign flag.
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kNotSign = kPL, //!< Not sign.
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kNegative = kMI, //!< Negative.
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kPositive = kPL, //!< Positive or zero.
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kOverflow = kVS, //!< Signed overflow.
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kNotOverflow = kVC, //!< Not signed overflow.
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kSignedLT = kLT, //!< Signed `a < b`.
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kSignedLE = kLE, //!< Signed `a <= b`.
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kSignedGT = kGT, //!< Signed `a > b`.
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kSignedGE = kGE, //!< Signed `a >= b`.
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kUnsignedLT = kLO, //!< Unsigned `a < b`.
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kUnsignedLE = kLS, //!< Unsigned `a <= b`.
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kUnsignedGT = kHI, //!< Unsigned `a > b`.
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kUnsignedGE = kHS, //!< Unsigned `a >= b`.
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kBTZero = kZero, //!< Tested bit is zero.
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kBTNotZero = kNotZero, //!< Tested bit is not zero.
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kAlways = kAL, //!< No condition code (always).
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kMaxValue = 0x0Fu //!< Maximum value of `CondCode`.
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};
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//! \cond
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static constexpr CondCode _reverseCondTable[] = {
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CondCode::kAL, // AL <- AL
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CondCode::kNA, // NA <- NA
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CondCode::kEQ, // EQ <- EQ
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CondCode::kNE, // NE <- NE
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CondCode::kLS, // LS <- CS
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CondCode::kHI, // HI <- LO
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CondCode::kMI, // MI <- MI
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CondCode::kPL, // PL <- PL
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CondCode::kVS, // VS <- VS
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CondCode::kVC, // VC <- VC
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CondCode::kLO, // LO <- HI
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CondCode::kCS, // CS <- LS
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CondCode::kLE, // LE <- GE
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CondCode::kGT, // GT <- LT
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CondCode::kLT, // LT <- GT
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CondCode::kGE // GE <- LE
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};
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//! \endcond
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//! Reverses a condition code (reverses the corresponding operands of a comparison).
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static ASMJIT_INLINE_NODEBUG constexpr CondCode reverseCond(CondCode cond) noexcept { return _reverseCondTable[uint8_t(cond)]; }
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//! Negates a condition code.
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static ASMJIT_INLINE_NODEBUG constexpr CondCode negateCond(CondCode cond) noexcept { return CondCode(uint8_t(cond) ^ uint8_t(1)); }
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//! Memory offset mode.
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//!
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//! Describes either fixed, pre-index, or post-index offset modes.
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enum class OffsetMode : uint32_t {
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//! Fixed offset mode (either no index at all or a regular index without a write-back).
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kFixed = 0u,
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//! Pre-index "[BASE, #Offset {, <shift>}]!" with write-back.
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kPreIndex = 1u,
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//! Post-index "[BASE], #Offset {, <shift>}" with write-back.
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kPostIndex = 2u
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};
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//! Shift operation predicate (ARM) describes either SHIFT or EXTEND operation.
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//!
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//! \note The constants are AsmJit specific. The first 5 values describe real constants on ARM32 and AArch64 hardware,
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//! however, the addition constants that describe extend modes are specific to AsmJit and would be translated to the
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//! AArch64 specific constants by the assembler.
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enum class ShiftOp : uint32_t {
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//! Shift left logical operation (default).
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//!
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//! Available to all ARM architectures.
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kLSL = 0x00u,
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//! Shift right logical operation.
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//!
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//! Available to all ARM architectures.
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kLSR = 0x01u,
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//! Shift right arithmetic operation.
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//!
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//! Available to all ARM architectures.
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kASR = 0x02u,
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//! Rotate right operation (AArch32 only).
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kROR = 0x03u,
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//! Rotate right with carry operation (encoded as `ShiftOp::kROR` with zero) (AArch32 only).
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kRRX = 0x04u,
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//! Shift left by filling low order bits with ones.
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kMSL = 0x05u,
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//! UXTN extend register operation (AArch64 only).
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kUXTB = 0x06u,
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//! UXTH extend register operation (AArch64 only).
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kUXTH = 0x07u,
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//! UXTW extend register operation (AArch64 only).
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kUXTW = 0x08u,
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//! UXTX extend register operation (AArch64 only).
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kUXTX = 0x09u,
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//! SXTB extend register operation (AArch64 only).
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kSXTB = 0x0Au,
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//! SXTH extend register operation (AArch64 only).
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kSXTH = 0x0Bu,
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//! SXTW extend register operation (AArch64 only).
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kSXTW = 0x0Cu,
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//! SXTX extend register operation (AArch64 only).
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kSXTX = 0x0Du
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// NOTE: 0xE and 0xF are used by memory operand to specify POST|PRE offset mode.
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};
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//! Represents ARM immediate shift operation type and value.
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class Shift {
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public:
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//! Shift operation.
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ShiftOp _op;
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//! Shift Value.
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uint32_t _value;
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//! Default constructed Shift is not initialized.
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ASMJIT_INLINE_NODEBUG Shift() noexcept = default;
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//! Copy constructor (default)
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ASMJIT_INLINE_NODEBUG constexpr Shift(const Shift& other) noexcept = default;
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//! Constructs Shift from operation `op` and shift `value`.
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ASMJIT_INLINE_NODEBUG constexpr Shift(ShiftOp op, uint32_t value) noexcept
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: _op(op),
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_value(value) {}
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//! Returns the shift operation.
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ASMJIT_INLINE_NODEBUG constexpr ShiftOp op() const noexcept { return _op; }
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//! Sets shift operation to `op`.
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ASMJIT_INLINE_NODEBUG void setOp(ShiftOp op) noexcept { _op = op; }
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//! Returns the shift amount.
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ASMJIT_INLINE_NODEBUG constexpr uint32_t value() const noexcept { return _value; }
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//! Sets shift amount to `value`.
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ASMJIT_INLINE_NODEBUG void setValue(uint32_t value) noexcept { _value = value; }
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};
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//! \}
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ASMJIT_END_SUB_NAMESPACE
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ASMJIT_BEGIN_SUB_NAMESPACE(a32)
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using namespace arm;
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//! Data type that can be encoded with AArch32 instruction identifier.
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//!
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//! \note Data types are frequently used with AArch32 SIMD instructions. For example `VMAX` instruction can
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//! use almost all datatypes in a form `VMAX.F32`, `VMAX.S16`, `VMAX.U32`, etc... Emitter automatically adds
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//! the required data type at emit level.
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enum class DataType : uint32_t {
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//! No data type specified (default for all general purpose instructions).
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kNone = 0,
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//! 8-bit signed integer, specified as `.s8` in assembly.
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kS8 = 1,
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//! 16-bit signed integer, specified as `.s16` in assembly.
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kS16 = 2,
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//! 32-bit signed integer, specified as `.s32` in assembly.
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kS32 = 3,
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//! 64-bit signed integer, specified as `.s64` in assembly.
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kS64 = 4,
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//! 8-bit unsigned integer, specified as `.u8` in assembly.
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kU8 = 5,
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//! 16-bit unsigned integer, specified as `.u16` in assembly.
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kU16 = 6,
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//! 32-bit unsigned integer, specified as `.u32` in assembly.
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kU32 = 7,
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//! 64-bit unsigned integer, specified as `.u64` in assembly.
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kU64 = 8,
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//! 16-bit floating point (half precision), specified as `.f16` in assembly.
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kF16 = 10,
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//! 32-bit floating point (single precision), specified as `.f32` in assembly.
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kF32 = 11,
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//! 64-bit floating point (double precision), specified as `.f64` in assembly.
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kF64 = 12,
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//! 8-bit polynomial.
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kP8 = 13,
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//! 16-bit BF16 floating point.
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kBF16 = 14,
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//! 64-bit polynomial.
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kP64 = 15,
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//! Maximum value of `DataType`.
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kMaxValue = 15
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};
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static ASMJIT_INLINE_NODEBUG uint32_t dataTypeSize(DataType dt) noexcept {
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static constexpr uint8_t table[] = { 0, 1, 2, 4, 8, 1, 2, 4, 8, 2, 4, 8, 1, 2, 8 };
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return table[size_t(dt)];
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}
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ASMJIT_END_SUB_NAMESPACE
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ASMJIT_BEGIN_SUB_NAMESPACE(a64)
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using namespace arm;
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ASMJIT_END_SUB_NAMESPACE
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#endif // ASMJIT_CORE_ARCHCOMMONS_H_INCLUDED
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